45 lines
1.6 KiB
C
45 lines
1.6 KiB
C
// Copyright 2023 Nick Brassel (@tzarc)
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// SPDX-License-Identifier: GPL-2.0-or-later
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///////////////////////////////////////////////////////////////////////////////
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// BEGIN: STM32 EFL Wear-leveling ECC fault handling
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//
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// Some STM32s have ECC checks for all flash memory access. Whenever there's an
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// ECC failure, the MCU raises the NMI interrupt. Whenever we receive such an
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// interrupt whilst reading the wear-leveling EEPROM area, we gracefully cater
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// for it, signalling the wear-leveling code that a failure has occurred.
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///////////////////////////////////////////////////////////////////////////////
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#include <ch.h>
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#include <chcore.h>
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#ifdef WEAR_LEVELING_EMBEDDED_FLASH
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# ifdef QMK_MCU_SERIES_STM32L4XX
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# define ECC_ERRORS_TRIGGER_NMI_INTERRUPT
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# define ECC_CHECK_REGISTER FLASH->ECCR
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# define ECC_CHECK_FLAG FLASH_ECCR_ECCD
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# endif // QMK_MCU_SERIES_STM32L4XX
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#endif // WEAR_LEVELING_EMBEDDED_FLASH
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#ifdef ECC_ERRORS_TRIGGER_NMI_INTERRUPT
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extern bool backing_store_allow_ecc_errors(void);
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extern void backing_store_signal_ecc_error(void);
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void NMI_Handler(void) {
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if ((ECC_CHECK_REGISTER) & (ECC_CHECK_FLAG)) {
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if (backing_store_allow_ecc_errors()) {
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(ECC_CHECK_REGISTER) = (ECC_CHECK_FLAG);
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backing_store_signal_ecc_error();
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return;
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}
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}
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chSysHalt("NMI");
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}
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#endif // ECC_ERRORS_TRIGGER_NMI_INTERRUPT
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///////////////////////////////////////////////////////////////////////////////
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// END: STM32 EFL Wear-leveling ECC fault handling
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///////////////////////////////////////////////////////////////////////////////
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