115 lines
3.9 KiB
C
115 lines
3.9 KiB
C
/*
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Copyright 2018 Massdrop Inc.
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "arm_atsam_protocol.h"
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uint16_t v_5v;
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uint16_t v_5v_avg;
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uint16_t v_con_1;
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uint16_t v_con_2;
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uint16_t v_con_1_boot;
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uint16_t v_con_2_boot;
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void ADC0_clock_init(void) {
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DBGC(DC_ADC0_CLOCK_INIT_BEGIN);
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MCLK->APBDMASK.bit.ADC0_ = 1; // ADC0 Clock Enable
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GCLK->PCHCTRL[ADC0_GCLK_ID].bit.GEN = GEN_OSC0; // Select generator clock
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GCLK->PCHCTRL[ADC0_GCLK_ID].bit.CHEN = 1; // Enable peripheral clock
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DBGC(DC_ADC0_CLOCK_INIT_COMPLETE);
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}
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void ADC0_init(void) {
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DBGC(DC_ADC0_INIT_BEGIN);
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// MCU
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PORT->Group[1].DIRCLR.reg = 1 << 0; // PB00 as input 5V
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PORT->Group[1].DIRCLR.reg = 1 << 1; // PB01 as input CON2
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PORT->Group[1].DIRCLR.reg = 1 << 2; // PB02 as input CON1
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PORT->Group[1].PMUX[0].bit.PMUXE = 1; // PB00 mux select B ADC 5V
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PORT->Group[1].PMUX[0].bit.PMUXO = 1; // PB01 mux select B ADC CON2
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PORT->Group[1].PMUX[1].bit.PMUXE = 1; // PB02 mux select B ADC CON1
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PORT->Group[1].PINCFG[0].bit.PMUXEN = 1; // PB01 mux ADC Enable 5V
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PORT->Group[1].PINCFG[1].bit.PMUXEN = 1; // PB01 mux ADC Enable CON2
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PORT->Group[1].PINCFG[2].bit.PMUXEN = 1; // PB02 mux ADC Enable CON1
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// ADC
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ADC0->CTRLA.bit.SWRST = 1;
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while (ADC0->SYNCBUSY.bit.SWRST) {
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DBGC(DC_ADC0_SWRST_SYNCING_1);
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}
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while (ADC0->CTRLA.bit.SWRST) {
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DBGC(DC_ADC0_SWRST_SYNCING_2);
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}
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// Clock divide
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ADC0->CTRLA.bit.PRESCALER = ADC_CTRLA_PRESCALER_DIV2_Val;
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// Averaging
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ADC0->AVGCTRL.bit.SAMPLENUM = ADC_AVGCTRL_SAMPLENUM_4_Val;
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while (ADC0->SYNCBUSY.bit.AVGCTRL) {
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DBGC(DC_ADC0_AVGCTRL_SYNCING_1);
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}
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if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_1_Val)
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ADC0->AVGCTRL.bit.ADJRES = 0;
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else if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_2_Val)
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ADC0->AVGCTRL.bit.ADJRES = 1;
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else if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_4_Val)
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ADC0->AVGCTRL.bit.ADJRES = 2;
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else if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_8_Val)
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ADC0->AVGCTRL.bit.ADJRES = 3;
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else
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ADC0->AVGCTRL.bit.ADJRES = 4;
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while (ADC0->SYNCBUSY.bit.AVGCTRL) {
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DBGC(DC_ADC0_AVGCTRL_SYNCING_2);
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}
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// Settling
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ADC0->SAMPCTRL.bit.SAMPLEN = 45; // Sampling Time Length: 1-63, 1 ADC CLK per
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while (ADC0->SYNCBUSY.bit.SAMPCTRL) {
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DBGC(DC_ADC0_SAMPCTRL_SYNCING_1);
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}
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// Load factory calibration data
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ADC0->CALIB.bit.BIASCOMP = ((*(uint32_t *)ADC0_FUSES_BIASCOMP_ADDR) & ADC0_FUSES_BIASCOMP_Msk) >> ADC0_FUSES_BIASCOMP_Pos;
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ADC0->CALIB.bit.BIASR2R = ((*(uint32_t *)ADC0_FUSES_BIASR2R_ADDR) & ADC0_FUSES_BIASR2R_Msk) >> ADC0_FUSES_BIASR2R_Pos;
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ADC0->CALIB.bit.BIASREFBUF = ((*(uint32_t *)ADC0_FUSES_BIASREFBUF_ADDR) & ADC0_FUSES_BIASREFBUF_Msk) >> ADC0_FUSES_BIASREFBUF_Pos;
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// Enable
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ADC0->CTRLA.bit.ENABLE = 1;
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while (ADC0->SYNCBUSY.bit.ENABLE) {
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DBGC(DC_ADC0_ENABLE_SYNCING_1);
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}
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DBGC(DC_ADC0_INIT_COMPLETE);
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}
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uint16_t adc_get(uint8_t muxpos) {
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ADC0->INPUTCTRL.bit.MUXPOS = muxpos;
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while (ADC0->SYNCBUSY.bit.INPUTCTRL) {
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}
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ADC0->SWTRIG.bit.START = 1;
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while (ADC0->SYNCBUSY.bit.SWTRIG) {
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}
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while (!ADC0->INTFLAG.bit.RESRDY) {
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}
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return ADC0->RESULT.reg;
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}
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