* gnu/packages/fpga.scm (yosys): New variable. Signed-off-by: Efraim Flashner <efraim@flashner.co.il>
191 lines
8 KiB
Scheme
191 lines
8 KiB
Scheme
;;; GNU Guix --- Functional package management for GNU
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;;; Copyright © 2016 Danny Milosavljevic <dannym@scratchpost.org>
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;;;
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;;; This file is part of GNU Guix.
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;;;
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;;; GNU Guix is free software; you can redistribute it and/or modify it
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;;; under the terms of the GNU General Public License as published by
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;;; the Free Software Foundation; either version 3 of the License, or (at
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;;; your option) any later version.
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;;;
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;;; GNU Guix is distributed in the hope that it will be useful, but
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;;; WITHOUT ANY WARRANTY; without even the implied warranty of
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;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;;; GNU General Public License for more details.
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;;;
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;;; You should have received a copy of the GNU General Public License
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;;; along with GNU Guix. If not, see <http://www.gnu.org/licenses/>.
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(define-module (gnu packages fpga)
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#:use-module ((guix licenses) #:prefix license:)
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#:use-module (guix packages)
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#:use-module (guix download)
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#:use-module (guix git-download)
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#:use-module (guix build-system gnu)
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#:use-module (guix build-system cmake)
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#:use-module (gnu packages)
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#:use-module (gnu packages pkg-config)
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#:use-module (gnu packages tcl)
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#:use-module (gnu packages readline)
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#:use-module (gnu packages python)
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#:use-module (gnu packages bison)
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#:use-module (gnu packages flex)
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#:use-module (gnu packages libffi)
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#:use-module (gnu packages zip)
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#:use-module (gnu packages perl)
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#:use-module (gnu packages ghostscript)
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#:use-module (gnu packages gawk)
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#:use-module (gnu packages version-control)
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#:use-module (gnu packages libftdi))
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(define-public abc
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(let ((commit "5ae4b975c49c")
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(revision "1"))
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(package
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(name "abc")
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(version (string-append "0.0-" revision "-" (string-take commit 9)))
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(source (origin
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(method url-fetch)
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(uri
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(string-append "https://bitbucket.org/alanmi/abc/get/" commit ".zip"))
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(file-name (string-append name "-" version "-checkout.zip"))
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(sha256
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(base32
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"1syygi1x40rdryih3galr4q8yg1w5bvdzl75hd27v1xq0l5bz3d0"))))
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(build-system gnu-build-system)
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(native-inputs
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`(("unzip" ,unzip)))
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(inputs
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`(("readline" ,readline)))
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(arguments
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`(#:tests? #f ; no check target
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#:phases
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(modify-phases %standard-phases
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(delete 'configure)
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(replace 'install
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(lambda* (#:key outputs #:allow-other-keys)
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(let* ((out (assoc-ref outputs "out"))
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(out-bin (string-append out "/bin")))
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(install-file "abc" out-bin)))))))
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(home-page "http://people.eecs.berkeley.edu/~alanmi/abc/")
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(synopsis "Sequential logic synthesis and formal verification")
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(description "ABC is a program for sequential logic synthesis and
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formal verification.")
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(license
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(license:non-copyleft "https://fedoraproject.org/wiki/Licensing:MIT#Modern_Variants")))))
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(define-public iverilog
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(package
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(name "iverilog")
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(version "10.1.1")
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(source (origin
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(method url-fetch)
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(uri
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(string-append "ftp://ftp.icarus.com/pub/eda/verilog/v10/"
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"verilog-" version ".tar.gz"))
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(sha256
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(base32
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"1nnassxvq30rnn0r2p85rkb2zwxk97p109y13x3vr365wzgpbapx"))))
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(build-system gnu-build-system)
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(native-inputs
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`(("flex" ,flex)
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("bison" ,bison)
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("ghostscript" ,ghostscript))) ; ps2pdf
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(home-page "http://iverilog.icarus.com/")
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(synopsis "FPGA Verilog simulation and synthesis tool")
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(description "Icarus Verilog is a Verilog simulation and synthesis tool.
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It operates as a compiler, compiling source code written in Verilog
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(IEEE-1364) into some target format.
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For batch simulation, the compiler can generate an intermediate form
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called vvp assembly.
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This intermediate form is executed by the ``vvp'' command.
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For synthesis, the compiler generates netlists in the desired format.")
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;; GPL2 only because of:
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;; - ./driver/iverilog.man.in
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;; - ./iverilog-vpi.man.in
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;; - ./tgt-fpga/iverilog-fpga.man
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;; - ./vvp/vvp.man.in
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;; Otherwise would be GPL2+.
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;; You have to accept both GPL2 and LGPL2.1+.
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(license (list license:gpl2 license:lgpl2.1+))))
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(define-public yosys
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(package
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(name "yosys")
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(version "0.6")
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(source (origin
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(method url-fetch)
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(uri
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(string-append "https://github.com/cliffordwolf/yosys/archive/"
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name "-" version ".tar.gz"))
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(sha256
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(base32
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"02j0c0m9dfyjccynalf0aggj6gy20k7iphpkg5cn6sdirlkv8gmx"))
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(file-name (string-append name "-" version "-checkout.tar.gz"))
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(modules '((guix build utils)))
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(snippet
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'(substitute* "Makefile"
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(("ABCREV = .*") "ABCREV = default\n")))))
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(build-system gnu-build-system)
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(arguments
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`(#:test-target "test"
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#:make-flags (list "CC=gcc"
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"CXX=g++"
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(string-append "PREFIX=" %output))
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#:phases
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(modify-phases %standard-phases
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(replace 'configure
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(lambda* (#:key inputs (make-flags '()) #:allow-other-keys)
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(zero? (apply system* "make" "config-gcc" make-flags))))
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(add-after 'configure 'prepare-abc
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(lambda* (#:key inputs #:allow-other-keys)
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(let* ((sourceabc (assoc-ref inputs "abc"))
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(sourcebin (string-append sourceabc "/bin"))
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(source (string-append sourcebin "/abc")))
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(mkdir-p "abc")
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(call-with-output-file "abc/Makefile"
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(lambda (port)
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(format port ".PHONY: all\nall:\n\tcp -f abc abc-default\n")))
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(copy-file source "abc/abc")
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(zero? (system* "chmod" "+w" "abc/abc")))))
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(add-before 'check 'fix-iverilog-references
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(lambda* (#:key inputs native-inputs #:allow-other-keys)
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(let* ((xinputs (or native-inputs inputs))
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(xdirname (assoc-ref xinputs "iverilog"))
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(iverilog (string-append xdirname "/bin/iverilog")))
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(substitute* '("./manual/CHAPTER_StateOfTheArt/synth.sh"
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"./manual/CHAPTER_StateOfTheArt/validate_tb.sh"
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"./techlibs/ice40/tests/test_bram.sh"
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"./techlibs/ice40/tests/test_ffs.sh"
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"./techlibs/xilinx/tests/bram1.sh"
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"./techlibs/xilinx/tests/bram2.sh"
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"./tests/bram/run-single.sh"
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"./tests/realmath/run-test.sh"
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"./tests/simple/run-test.sh"
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"./tests/techmap/mem_simple_4x1_runtest.sh"
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"./tests/tools/autotest.sh"
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"./tests/vloghtb/common.sh")
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(("if ! which iverilog") "if ! true")
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(("iverilog ") (string-append iverilog " "))
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(("iverilog_bin=\".*\"") (string-append "iverilog_bin=\""
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iverilog "\"")))
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#t))))))
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;; TODO add xdot [patch the path to it here] as soon as I find out where it is.
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(native-inputs
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`(("pkg-config" ,pkg-config)
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("python" ,python)
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("bison" ,bison)
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("flex" ,flex)
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("gawk" , gawk) ; for the tests and "make" progress pretty-printing
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("tcl" ,tcl) ; tclsh for the tests
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("iverilog" ,iverilog))) ; for the tests
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(inputs
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`(("tcl" ,tcl)
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("readline" ,readline)
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("libffi" ,libffi)
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("abc" ,abc)))
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(home-page "http://www.clifford.at/yosys/")
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(synopsis "FPGA Verilog RTL synthesizer")
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(description "Yosys synthesizes Verilog-2005.")
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(license license:isc)))
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