109 lines
2.8 KiB
Diff
109 lines
2.8 KiB
Diff
This GCC patch is from the ath9k-htc-firmware repository (version 1.3.2).
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Not applying it (apparently) leads to miscompiled firmware, and loading it
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fails with a "Target is unresponsive" message from the 'ath9k_htc' module.
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From c7162b8a3db42e7faf47606d3aa3dd61e64aea17 Mon Sep 17 00:00:00 2001
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From: Sujith Manoharan <c_manoha@qca.qualcomm.com>
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Date: Mon, 7 Jan 2013 16:06:28 +0530
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Subject: [PATCH] gcc: AR9271/AR7010 config
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Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
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---
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include/xtensa-config.h | 36 +++++++++++++++++-------------------
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1 file changed, 17 insertions(+), 19 deletions(-)
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diff --git a/include/xtensa-config.h b/include/xtensa-config.h
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index 30f4f41..fe9b051 100644
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--- a/include/xtensa-config.h
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+++ b/include/xtensa-config.h
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@@ -44,10 +44,7 @@
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#define XCHAL_HAVE_L32R 1
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#undef XSHAL_USE_ABSOLUTE_LITERALS
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-#define XSHAL_USE_ABSOLUTE_LITERALS 0
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-
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-#undef XSHAL_HAVE_TEXT_SECTION_LITERALS
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-#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
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+#define XSHAL_USE_ABSOLUTE_LITERALS 1
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#undef XCHAL_HAVE_MAC16
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#define XCHAL_HAVE_MAC16 0
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@@ -59,10 +56,10 @@
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#define XCHAL_HAVE_MUL32 1
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#undef XCHAL_HAVE_MUL32_HIGH
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-#define XCHAL_HAVE_MUL32_HIGH 0
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+#define XCHAL_HAVE_MUL32_HIGH 1
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#undef XCHAL_HAVE_DIV32
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-#define XCHAL_HAVE_DIV32 1
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+#define XCHAL_HAVE_DIV32 0
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#undef XCHAL_HAVE_NSA
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#define XCHAL_HAVE_NSA 1
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@@ -103,8 +100,6 @@
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#undef XCHAL_HAVE_FP_RSQRT
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#define XCHAL_HAVE_FP_RSQRT 0
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-#undef XCHAL_HAVE_DFP_accel
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-#define XCHAL_HAVE_DFP_accel 0
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#undef XCHAL_HAVE_WINDOWED
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#define XCHAL_HAVE_WINDOWED 1
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@@ -119,32 +114,32 @@
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#undef XCHAL_ICACHE_SIZE
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-#define XCHAL_ICACHE_SIZE 16384
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+#define XCHAL_ICACHE_SIZE 0
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#undef XCHAL_DCACHE_SIZE
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-#define XCHAL_DCACHE_SIZE 16384
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+#define XCHAL_DCACHE_SIZE 0
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#undef XCHAL_ICACHE_LINESIZE
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-#define XCHAL_ICACHE_LINESIZE 32
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+#define XCHAL_ICACHE_LINESIZE 16
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#undef XCHAL_DCACHE_LINESIZE
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-#define XCHAL_DCACHE_LINESIZE 32
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+#define XCHAL_DCACHE_LINESIZE 16
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#undef XCHAL_ICACHE_LINEWIDTH
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-#define XCHAL_ICACHE_LINEWIDTH 5
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+#define XCHAL_ICACHE_LINEWIDTH 4
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#undef XCHAL_DCACHE_LINEWIDTH
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-#define XCHAL_DCACHE_LINEWIDTH 5
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+#define XCHAL_DCACHE_LINEWIDTH 4
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#undef XCHAL_DCACHE_IS_WRITEBACK
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-#define XCHAL_DCACHE_IS_WRITEBACK 1
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+#define XCHAL_DCACHE_IS_WRITEBACK 0
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#undef XCHAL_HAVE_MMU
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#define XCHAL_HAVE_MMU 1
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#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE
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-#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12
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+#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29
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#undef XCHAL_HAVE_DEBUG
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@@ -157,8 +152,11 @@
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#define XCHAL_NUM_DBREAK 2
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#undef XCHAL_DEBUGLEVEL
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-#define XCHAL_DEBUGLEVEL 6
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+#define XCHAL_DEBUGLEVEL 4
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+
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+#undef XCHAL_EXCM_LEVEL
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+#define XCHAL_EXCM_LEVEL 3
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#undef XCHAL_MAX_INSTRUCTION_SIZE
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#define XCHAL_MAX_INSTRUCTION_SIZE 3
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--
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1.8.1
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