48 lines
1.6 KiB
Diff
48 lines
1.6 KiB
Diff
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https://pagure.io/libaio/pull-request/23
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From f68c69b6cbc1260a6034997d5f146e3d0a197ed8 Mon Sep 17 00:00:00 2001
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From: Xiongchuan Tan <xc-tan@outlook.com>
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Date: Jun 28 2022 15:53:38 +0000
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Subject: As of June 28th, 2022, the RISC-V spec[1] reserves the PTE permission bit
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combination of "write+!read", and the kernel would have incoherent behavior in
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the last test case of "harness/cases/5.t". Since it leads to undefined behavior,
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until further spec update, this test case should be disabled for RISC-V.
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A patch to disallow such permission in mmap() can be found here[2].
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[1]: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf
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[2]: https://www.spinics.net/lists/kernel/msg4412421.html
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---
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diff --git a/harness/cases/5.t b/harness/cases/5.t
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index b0a7c56..8d6c959 100644
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--- a/harness/cases/5.t
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+++ b/harness/cases/5.t
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@@ -37,6 +37,14 @@ int test_main(void)
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status |= attempt_rw(rwfd, buf, SIZE, 0, READ, -EFAULT);
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res = munmap(buf, page_size); assert(res == 0);
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+
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+ /* As of June 28th, 2022, the RISC-V spec Volume 2 Section 4.3
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+ * version "20211203 Privileged Architecture v1.12, Ratified"
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+ * reserves the usage of the PTE permission bit combination of
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+ * "write+!read", so the next test leads to undefined behavior
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+ * and should be disabled. */
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+#ifndef __riscv
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+
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buf = mmap(0, page_size, PROT_WRITE, MAP_SHARED, rwfd, 0);
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assert(buf != (char *)-1);
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@@ -48,6 +56,8 @@ int test_main(void)
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status |= attempt_rw(rwfd, buf, SIZE, 0, READ, SIZE);
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status |= attempt_rw(rwfd, buf, SIZE, 0, WRITE, res);
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+#endif
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+
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return status;
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}
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